IP CORES PORTFOLIO

Esencia IP cores are among the best performance, low gate count IPs available in the market today. Each of these IP cores can be uniquely configured to meet the any customer requirements

DSP Communications domain

  • FFT/1024/512 Low latency, dynamically configurable as 1024 or 512 points FFT and IFFT. Ideal for WiMax and MIMO applications. Detailed datasheet can be downloaded from pdfhere.
  • FFT 64/128: Low latency, 64 point FFT and IFFT. Parameterized bit widths and fixed point options. Supports flushing and re-starting the FFT operation instantly. Detailed datasheet can be downloaded from pdfhere.
  • Viterbi Decoder: Viterbi Algorithm for 802.11 a/b/g standard. Low gate count implementation. Option to optimize on flush latency with additional hardware. Detailed datasheet can be downloaded from pdfhere.

Security domain (Encryption and Authentication)

  • AES: High speed Advanced Encryption Standard. Supports AES FIPS 197 encryption and decryption. Detailed datasheet can be downloaded from here.
  • DES: Low-gate count Data Encryption Standard. Supports both encryption and decryption. Can be configured to implement Triple-DES. Detailed datasheet can be downloaded from pdfhere.
  • SHA-1 Hash: High speed data authentication. This IP core supports the Secure Hash Algorithm described in RFC 3174. Detailed datasheet can be downloaded from pdfhere.
  • MD5: High Speed data authentication. This IP core supports the MD5 Secure Hash Algorithm described in RFC 1321. Detailed datasheet can be downloaded from pdfhere.
  • ARC4: Multi-threaded stream ciphering algorithm. This IP core supports simultaneous encryption/decryption of multiple independent sessions in a time-multiplexed fashion. Detailed datasheet can be downloaded from pdfhere.